The invention relates to a semiconductor component with connecting elements and a method for producing the same. The semiconductor component has the connecting elements on a semiconductor chip made from a semiconductor wafer with discrete semiconductor components for surface mounting on a superordinate circuit carrier. In this case, the semiconductor component has a coplanar area having top sides of the connecting elements and a plastics composition. The connecting elements are provided on contact areas of the semiconductor chip or semiconductor component.
The miniaturization of discrete semiconductor components, such as diodes and transistors, and the price pressure on such standardized semiconductor components constantly demand new and revised solutions for the housing construction. The housing construction makes a distinction between housings based on a flat conductor leadframe, such as, for example, SOT, SOD, SC, and/or TSFP housings, and flat-conductor-free housings, such as, for example, the TSLP housing. These current solutions for providing housing constructions for discrete semiconductor components have the disadvantage that they are based on processes such as die bonding and wire bonding. In this case, it is disadvantageous that it is necessary to provide corresponding semiconductor chip pads for the application of the semiconductor chips in the case of die bonding and corresponding contact pads for fitting the bonding wires in the case of wire bonding on a carrier.
These components reduce the possibility of improving the housings with regard to miniaturization. Thus, the housing height cannot be reduced arbitrarily since the thickness of the contact pads or the thickness of the semiconductor chip contact areas and the thickness of the semiconductor chip, and also the bonding wire loop height and the height of the plastic housing composition for embedding the bonding wires have to be taken into account. Limits are imposed on the miniaturization of the lateral dimensions in the case of the discrete semiconductor components since it is necessary to take account of sufficient space for the tolerances of wire bonding on the semiconductor chips, the tolerances of the lengths of the bonding wires and the tolerances for the wall thickness of the moulding compositions. As a result, in the case of discrete semiconductor components, the possibility for miniaturization is exhausted at dimensions of below half a millimeter with regard to length, width and height of the packaged semiconductor component.
In the case of TSLP housings, a final process of electroless chemical deposition of NiAu has hitherto been provided, which may bring about the risk of embrittlement of the surface-mountable external contacts since nickel tends towards the formation of brittle phases and thus constitutes a reliability problem. Under certain circumstances, the known wafer level packaging is also associated with a reliability problem, especially if active surface regions of the semiconductor chips and/or the rear sides thereof are not protected by a plastic housing composition.
In the case of surface-mountable BGA housings, a particular reliability problem is posed by the requirement for wiring substrates and underfill materials which have to compensate for and fill the distance to superordinate circuit carriers in order to reduce thermal stresses, which, furthermore, demands an additional space requirement and expensive production methods.
The document U.S. Pat. No. 6,197,613 B1 discloses a method for forming a housing based on a semiconductor wafer, which involves firstly providing a silicon wafer having a multiplicity of integrated circuit chips formed on the top side of the semiconductor wafer. Each of the integrated circuit chips has I/O contact areas, at least on a top side, which are not arranged in freely accessible fashion but rather in an elastic insulating layer. These contact areas are electrically connected to solder balls as flip-chip contacts via through contacts through the elastic insulating layer and via interconnects on the elastic layer. The semiconductor components of the order of magnitude of semiconductor chips that are produced by this method have the disadvantage that their housing height cannot be reduced arbitrarily due to the solder ball and the elastic layer arranged underneath.
The document U.S. Pat. No. 6,518,097 B1 discloses a method for producing flip-chip housings based on a semiconductor wafer using an anisotropically conductive adhesive. For this purpose, a bonding hump free of solder material, such as a bonding hump made of gold or a nickel/gold bonding hump deposited in electroless fashion, is produced on the contact areas of each semiconductor chip of a semiconductor wafer. An anisotropically conductive adhesive solution or a film is arranged on the wafer, and the semiconductor wafer is subsequently separated into individual semiconductor chips.
Each of the semiconductor chips is mechanically or electrically connected to a substrate by means of the anisotropically conductive adhesive. This method has the disadvantage that the semiconductor chips cannot be connected to a substrate in a solderable manner, rather the anisotropically conductive adhesive or an anisotropically conductive film is required for this purpose, which restricts both the method costs and the usability of such a semiconductor component for discrete semiconductor components.
For these and other reasons, there is a need for the present invention.